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PNX2000
Audio video input processor
Rev. 03 - 23 August 2004 Product data
1. General description
The PNX2000 is a companion IC for use with the NexperiaTM 1 digital video home entertainment engines such as PNX8526 and PNX8550. The PNX2000 is always used in combination with the PNX3000. PNX2000 is intended for mid to high-end analog and hybrid TV sets, performing input decoding of single stream analog audio and single stream analog video signals. In addition, the PNX2000 is used for decoding and presentation of all audio output streams in the system. Figure 1 shows a block diagram of the device.
2. Features
Detection of PAL, NTSC or SECAM, and various 1fH and 2fH component video input sources. Full support for 1fH and 2fH video sources; progressive and interlaced. Decoding for global VBI Standards (WST, WSS, VPS, CC, VITC). ITU-656 output interface. Global multi-standard audio demodulation and decoding. Dolby Pro Logic IITM 2 multi-channel audio decoding and post-processing. Advanced fully programmable audio post-processing functions, including psychoacoustic spatial algorithms for optimal loudspeaker matching.
3. Applications
Analog TV receivers. Hybrid TV receivers. DVD recorders. VCRs.
1. 2.
Nexperia is a trademark of Koninklijke Philips Electronics N.V.
Dolby is a trademark of Dolby Laboratories
Philips Semiconductors
PNX2000
Audio video input processor
4. Ordering information
Table 1: Ordering information Package name LQFP144 Description plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm Version SOT486-1 Type number PNX2000HL
5. Block diagram
DLINK2 DLINK1 DLINK3
PNX2000
audio data SIF or L/R I2D
video data CVBS, Y/C, YUV 54 MHz clock 27 Msps or 54 Msps
I2C-bus
I2C-BUS HSYNC VIDDEC HSYNC/ VSYNC
INT
GTU
DCU 13.5 MHz or 27 MHz Xtal CLOCKS
ITU-656 DEMDEC DSP 6x I2S-bus outputs 6x I2S-bus inputs PI-bus AUDIO DSP x4 x6 x2 BCU
mce559
PNX3000 interface (2 stereo or 4 mono)
ITU-656 1fH or 2fH 10-bit data
Fig 1. Block diagram
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Product data
Rev. 03 - 23 August 2004
2 of 31
Philips Semiconductors
PNX2000
Audio video input processor
6. Pinning information
6.1 Pinning
144 109 108
1
PNX2000HL
36 37 72
73
001aaa287
Fig 2. Pin configuration
6.1.1 Pin description
Table 2 describes acronyms used in the pin tables:
Table 2: Acronym 3V 5VT Z TTL TTL-H CMOS IA ID OD OA IOA IOD GA SA SD OSCIN OSCOUT OSCGND Acronym description Description 3.3 V LVCMOS 5 V tolerant inputs 3-state TTL logic TTL with hysteresis CMOS logic Input Analog Input Digital Output Digital Output Analog I/O Analog I/O Digital Ground Analog Supply Analog Supply Digital Crystal Oscillator Input Crystal Oscillator Output Crystal Oscillator Ground
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Product data
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Philips Semiconductors
PNX2000
Audio video input processor
Pins in numerical sequence Type GD IA IA IA IA IA IA IA IA IA IA IA IA SD ID IA IA OD ID ID SD SD GA IOD IOD OD n.c. OSCVDD OSCIN OSCOUT OSCGND Description I2D digital ground analog differential data link 1 positive termination analog differential data link 1 negative termination analog differential strobe link 1 positive termination analog differential strobe link 1 negative termination analog differential data link 2 positive termination analog differential data link 2 negative termination analog differential strobe link 2 positive termination analog differential strobe link 2 negative termination analog differential data link 3 positive termination analog differential data link 3 negative termination analog differential strobe link 3 positive termination analog differential strobe link 3 negative termination I2D digital 1.8 V supply voltage I2C-bus address select (internal pull-down); TTL; 5VT horizontal sync (external); fastblanking signal from SCART horizontal sync (external); fastblanking signal from SCART horizontal and vertical sync information to PNX3000; CMOS vertical sync (external); TTL; 5VT vertical sync (external); TTL; 5VT DTC 3.3 V supply voltage DTC 1.8 V supply voltage DTC analog ground I2C-bus clock; TTL; Z; 5VT I2C-bus data; TTL; Z; 5VT 3.3 V ground 1.8 V ground 1.8 V supply voltage 13.5 MHz or 27 MHz to PNX3000; CMOS 3.3 V supply voltage phase locked loop 1.8 V supply voltage not connected 1.8 V supply voltage 1.8 V ground 1.8 V crystal oscillator supply voltage crystal oscillator input crystal oscillator output crystal oscillator ground
Table 3: Pin 1 2 3 4 5 7 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Symbol VSSD(I2D) DLINK1DP DLINK1DN DLINK1SP DLINK1SN DLINK2DP DLINK2DN DLINK2SP DLINK2SN DLINK3DP DLINK3DN DLINK3SP DLINK3SN VDDD(I2D) I2C_ADR HSYNCFBL1 HSYNCFBL2 HVINFO VSYNC1 VSYNC2 VDD3(DTC) VDDD(DTC) VSS(DTC) I2C_SCL I2C_SDA VSSE VSS VDDI MPIFCLK VDDE VDDA(PLL) VDDI VSS VDDA(XTAL) XIN XOUT XGND
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Product data
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PNX2000
Audio video input processor
Pins in numerical sequence...continued Type IA ID OD OD ID OD OD OD OD OD OD OD OD OD OD OD OD OD OD OD OD OD OD OD OD IOD IOD Description 3.3 V ground 1.8 V supply voltage 1.8 V ground 1.8 V supply voltage for KSFRAMs and KROMs external reset input selects between using an external reset input or using internal POR; TTL; 5VT reserved; CMOS interrupt line output; Z; 5VT 3.3 V supply voltage reserved; TTL; 5VT digital video output clock; CMOS; Z digital video data valid; CMOS; Z 1.8 V supply voltage 1.8 V ground digital video output state 0; CMOS; Z digital video output state 1; CMOS; Z digital video output state 2; CMOS; Z digital video output state 3; CMOS; Z 3.3 V ground digital video output state 4; CMOS; Z digital video output state 5; CMOS; Z digital video output state 6; CMOS; Z digital video output state 7; CMOS; Z digital video output state 8; CMOS; Z digital video output state 9; CMOS; Z 3.3 V supply voltage 1.8 V supply voltage 1.8 V ground I2S-bus data-out channel 3; CMOS I2S-bus word select channel 3; CMOS I2S-bus bit clock channel 3; CMOS 3.3 V ground I2S-bus data out channel 6; CMOS I2S-bus data out channel 5; CMOS I2S-bus data out channel 4; CMOS I2S-bus data out channel 2; CMOS I2S-bus data out channel 1; CMOS I2S-bus system word select; TTL-H; CMOS I2S-bus system bit clock; TTL-H; CMOS 1.8 V supply voltage
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Table 3: Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
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Symbol VSSE VDDI VSS VDDM RESET_N RESET_SEL DCLK INTOUT VDDE LL_CLK DVO_CLK DVO_VALID VDDI VSS DVO_DATA_0 DVO_DATA_1 DVO_DATA_2 DVO_DATA_3 VSSE DVO_DATA_4 DVO_DATA_5 DVO_DATA_6 DVO_DATA_7 DVO_DATA_8 DVO_DATA_9 VDDE VDDI VSS I2S_OUT_SD3 I2S_OUT_SD3_WS I2S_OUT_SD3_SCK VSSE I2S_OUT_SD6 I2S_OUT_SD5 I2S_OUT_SD4 I2S_OUT_SD2 I2S_OUT_SD1 I2S_WS_SYS I2S_SCK_SYS VDDI
Product data
Rev. 03 - 23 August 2004
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Philips Semiconductors
PNX2000
Audio video input processor
Pins in numerical sequence...continued Type ID ID ID ID ID ID OD n.c. ID OD ID ID ID GD SD SA SA OA GA GA OA SA SA OA GA GA OA SA Description 1.8 V ground 3.3 V supply voltage I2S-bus data in channel 6; TTL; 5VT I2S-bus data in channel 5; TTL; 5VT I2S-bus data in channel 4; TTL; 5VT I2S-bus data in channel 3; TTL; 5VT I2S-bus data in channel 2; TTL; 5VT I2S-bus data in channel 1; TTL; 5VT Used for 128 fs or 256 fs clock output to external audio DAC; CMOS. not connected 3.3 V supply voltage JTAG test data in; TTL-H; 5VT JTAG test data out; CMOS JTAG test clock; TTL-H; 5VT JTAG test mode select; TTL-H; 5VT JTAG reset (active low); TTL-H; 5VT 1.8 V supply voltage 1.8 V ground 3.3 V ground audio DAC 1.8 V digital ground audio DAC 1.8 V digital supply voltage audio DAC 3.3 V supply voltage Positive analog reference derived via emitter follower from PNX3000 V_SND pin. analog audio output 1 Negative analog reference star connected at PNX3000. Negative analog reference star connected at PNX3000. analog audio output 2 Positive analog reference derived via emitter follower from PNX3000 V_SND pin. Positive analog reference derived via emitter follower from PNX3000 V_SND pin. analog audio output 3 Negative analog reference star connected at PNX3000. Negative analog reference star connected at PNX3000. analog audio output 4 Positive analog reference derived via emitter follower from PNX3000 V_SND pin.
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Table 3: Pin 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 VSS
Symbol VDDE I2S_IN_SD6 I2S_IN_SD5 I2S_IN_SD4 I2S_IN_SD3 I2S_IN_SD2 I2S_IN_SD1 ADAC_CLK VDDE TDI TDO TCK TMS TRST_N VDDI VSS VSSE VSS(ADAC) VDDD(ADAC) VDDA(ADAC) ADAC1_P ADAC1 ADAC1_N ADAC2_N ADAC2 ADAC2_P ADAC3_P ADAC3 ADAC3_N ADAC4_N ADAC4 ADAC4_P
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Product data
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Philips Semiconductors
PNX2000
Audio video input processor
Pins in numerical sequence...continued Type SA OA GA GA OA SA SA OA GA GA OA SA SA OA GA GA OA SA SA OA GA GA OA SA Description Positive analog reference derived via emitter follower from PNX3000 V_SND pin. analog audio output 5 Negative analog reference star connected at PNX3000. Negative analog reference star connected at PNX3000. analog audio output 6 Positive analog reference derived via emitter follower from PNX3000 V_SND pin. Positive analog reference derived via emitter follower from PNX3000 V_SND pin. analog audio output 7 Negative analog reference star connected at PNX3000. Negative analog reference star connected at PNX3000. analog audio output 8 Positive analog reference derived via emitter follower from PNX3000 V_SND pin. Positive analog reference derived via emitter follower from PNX3000 V_SND pin. analog audio output 9 Negative analog reference star connected at PNX3000. Negative analog reference star connected at PNX3000. analog audio output 10 Positive analog reference derived via emitter follower from PNX3000 V_SND pin. Positive analog reference derived via emitter follower from PNX3000 V_SND pin. analog audio output 11 Negative analog reference star connected at PNX3000. Negative analog reference star connected at PNX3000. analog audio output 12 Positive analog reference derived via emitter follower from PNX3000 V_SND pin. 1.8 V ground 1.8 V supply voltage for KSFRAMs and KROMs 3.3 V supply voltage
Table 3: Pin 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141
Symbol ADAC5_P ADAC5 ADAC5_N ADAC6_N ADAC6 ADAC6_P ADAC7_P ADAC7 ADAC7_N ADAC8_N ADAC8 ADAC8_P ADAC9_P ADAC9 ADAC9_N ADAC10_N ADAC10 ADAC10_P ADAC11_P ADAC11 ADAC11_N ADAC12_N ADAC12 ADAC12_P VSS VDDM VDDE
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Product data
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Philips Semiconductors
PNX2000
Audio video input processor
Pins in numerical sequence...continued Type Description 3.3 V ground 3.3 V supply voltage 3.3 V ground
Table 3: Pin 142 143 144
Symbol VSSE VDDE VSSE
In the tables that follow, signals of the PNX2000 have been sorted by functional group. For quick reference Table 4 identifies each functional group and associated table.
Table 4: I2D-bus AUDIO I2S-bus VIDDEC ITU-656 JTAG I2C-bus CLOCK GTU RESET DIGITAL SUPPLY ANALOG SUPPLY Table 5: Symbol DLINK1DP DLINK1DN DLINK1SP DLINK1SN DLINK2DP DLINK2DN DLINK2SP DLINK2SN DLINK3DP DLINK3DN DLINK3SP DLINK3SN Table 6: Symbol ADAC1 ADAC2 ADAC3 ADAC4
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Signal groups Table number Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16
Functional group
I2D pins Pin 2 3 4 5 7 8 9 10 12 13 14 15 Type IA IA IA IA IA IA IA IA IA IA IA IA Description analog differential data link 1 positive termination analog differential data link 1 negative termination analog differential strobe link 1 positive termination analog differential strobe link 1 negative termination analog differential data link 2 positive termination analog differential data link 2 negative termination analog differential strobe link 2 positive termination analog differential strobe link 2 negative termination analog differential data link 3 positive termination analog differential data link 3 negative termination analog differential strobe link 3 positive termination analog differential strobe link 3 negative termination
Audio pins Pin 104 107 110 113 Type OA OA OA OA Description analog audio output 1 analog audio output 2 analog audio output 3 analog audio output 4
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Product data
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Philips Semiconductors
PNX2000
Audio video input processor
Audio pins...continued Pin 116 119 122 125 128 131 134 137 103 105 108 106 109 111 114 112 115 117 120 118 121 123 126 124 127 129 132 130 133 135 138 136 Type OA OA OA OA OA OA OA OA SA GA SA GA SA GA SA GA SA GA SA GA SA GA SA GA SA GA SA GA SA GA SA GA Description analog audio output 5 analog audio output 6 analog audio output 7 analog audio output 8 analog audio output 9 analog audio output 10 analog audio output 11 analog audio output 12 Positive analog reference derived via emitter follower from PNX3000 V_SND pin. Negative analog reference star connected at PNX3000. Positive analog reference derived via emitter follower from PNX3000 V_SND pin. Negative analog reference star connected at PNX3000. Positive analog reference derived via emitter follower from PNX3000 V_SND pin. Negative analog reference star connected at PNX3000. Positive analog reference derived via emitter follower from PNX3000 V_SND pin. Negative analog reference star connected at PNX3000. Positive analog reference derived via emitter follower from PNX3000 V_SND pin. Negative analog reference star connected at PNX3000. Positive analog reference derived via emitter follower from PNX3000 V_SND pin. Negative analog reference star connected at PNX3000. Positive analog reference derived via emitter follower from PNX3000 V_SND pin. Negative analog reference star connected at PNX3000. Positive analog reference derived via emitter follower from PNX3000 V_SND pin. Negative analog reference star connected at PNX3000. Positive analog reference derived via emitter follower from PNX3000 V_SND pin. Negative analog reference star connected at PNX3000. Positive analog reference derived via emitter follower from PNX3000 V_SND pin. Negative analog reference star connected at PNX3000. Positive analog reference derived via emitter follower from PNX3000 V_SND pin. Negative analog reference star connected at PNX3000. Positive analog reference derived via emitter follower from PNX3000 V_SND pin. Negative analog reference star connected at PNX3000.
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Table 6: Symbol ADAC5 ADAC6 ADAC7 ADAC8 ADAC9 ADAC10 ADAC11 ADAC12 ADAC1_P ADAC1_N ADAC2_P ADAC2_N ADAC3_P ADAC3_N ADAC4_P ADAC4_N ADAC5_P ADAC5_N ADAC6_P ADAC6_N ADAC7_P ADAC7_N ADAC8_P ADAC8_N ADAC9_P ADAC9_N ADAC10_P ADAC10_N ADAC11_P ADAC11_N ADAC12_P ADAC12_N
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Philips Semiconductors
PNX2000
Audio video input processor
I2S-bus pins Pin 88 87 86 85 84 83 77 76 75 74 73 71 70 69 79 78 89 Type ID ID ID ID ID ID OD OD OD OD OD OD OD OD IOD IOD OD Description I2S-bus data in channel 1; TTL; 5VT I2S-bus data in channel 2; TTL; 5VT I2S-bus data in channel 3; TTL; 5VT I2S-bus data in channel 4; TTL; 5VT I2S-bus data in channel 5; TTL; 5VT I2S-bus data in channel 6; TTL; 5VT I2S-bus data out channel 1; CMOS I2S-bus data out channel 2; CMOS I2S-bus data out channel 4; CMOS I2S-bus data out channel 5; CMOS I2S-bus data out channel 6; CMOS I2S-bus bit clock channel 3; CMOS I2S-bus word select channel 3; CMOS I2S-bus data-out channel 3; CMOS I2S-bus system bit clock; TTL-H; CMOS I2S-bus system word select; TTL-H; CMOS Used for 128 fs or 256 fs clock output to external audio DAC; CMOS.
Table 7: Symbol
I2S_IN_SD1 I2S_IN_SD2 I2S_IN_SD3 I2S_IN_SD4 I2S_IN_SD5 I2S_IN_SD6 I2S_OUT_SD1 I2S_OUT_SD2 I2S_OUT_SD4 I2S_OUT_SD5 I2S_OUT_SD6 I2S_OUT_SD3_SCK I2S_OUT_SD3_WS I2S_OUT_SD3 I2S_SCK_SYS I2S_WS_SYS ADAC_CLK
Table 8: Symbol HVINFO
VIDDEC pins Pin 20 18 19 21 22 Type OD IA IA ID ID Description horizontal and vertical sync information to PNX3000; CMOS horizontal sync (external); fastblanking signal from SCART horizontal sync (external); fastblanking signal from SCART vertical sync (external); TTL; 5VT vertical sync (external); TTL; 5VT
HSYNCFBL1 HSYNCFBL2 VSYNC1 VSYNC2 Table 9: Symbol DVO_DATA_0 DVO_DATA_1 DVO_DATA_2 DVO_DATA_3 DVO_DATA_4 DVO_DATA_5 DVO_DATA_6 DVO_DATA_7 DVO_DATA_8 DVO_DATA_9
ITU-656 pins Pin 55 56 57 58 60 61 62 63 64 65 Type OD OD OD OD OD OD OD OD OD OD Description digital video output state 0; CMOS; Z digital video output state 1; CMOS; Z digital video output state 2; CMOS; Z digital video output state 3; CMOS; Z digital video output state 4; CMOS; Z digital video output state 5; CMOS; Z digital video output state 6; CMOS; Z digital video output state 7; CMOS; Z digital video output state 8; CMOS; Z digital video output state 9; CMOS; Z
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PNX2000
Audio video input processor
ITU-656 pins...continued Pin 52 51 50 Type OD OD ID Description digital video data valid; CMOS; Z digital video output clock; CMOS; Z reserved; TTL; 5VT [1]
Table 9: Symbol
DVO_VALID DVO_CLK LL_CLK
[1]
It is recommended to bias this pad with a 10 k resistor
Table 10: Symbol TDO TDI TCK TRST_N [1] TMS
[1]
JTAG pins Pin 93 92 94 96 95 Type OD ID ID ID ID Description JTAG test data out; CMOS JTAG test data in; TTL-H; 5VT JTAG test clock; TTL-H; 5VT JTAG reset (active low); TTL-H; 5VT JTAG test mode select; TTL-H; 5VT
It is recommended to pull-down TRST_N with a 10 k resistor. This ensures correct reset state of internal TAP circuitry and correct POR of the device within defined state machine.
Table 11: Symbol I2C_SDA I2C_SCL I2C_ADR Table 12: Symbol MPIFCLK DCLK XIN XOUT XGND Table 13: Symbol INTOUT Table 14: Symbol RESET_N
I2C-bus pins Pin 27 26 17 Clock pins Pin 31 47 38 39 40 GTU pins Pin 48 Reset pins Pin 45 46 Type IA ID Description external reset input selects between using an external reset input or using internal POR; TTL; 5VT HIGH = internal reset LOW = external reset Type OD Description interrupt line output; Z; 5VT Type OD OD OSCIN OSCOUT OSCGND Description 13.5 MHz or 27 MHz to PNX3000; CMOS reserved; CMOS crystal oscillator input crystal oscillator output crystal oscillator ground Type IOD IOD ID Description I2C-bus data; TTL; Z; 5VT I2C-bus clock; TTL; Z; 5VT I2C-bus address select (internal pull-down); TTL; 5VT
RESET_SEL
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PNX2000
Audio video input processor
Digital supply pins Pin 32,49,66, 82,91, 141,143 28,41,59, 72,99, 142,144 Type Description GD SD GD SD SD SD 3.3 V supply voltage 3.3 V ground 1.8 V supply voltage 1.8 V ground 1.8 V supply voltage for KSFRAMs and KROMs I2D digital ground I2D digital 1.8 V supply voltage audio DAC 1.8 V digital ground audio DAC 1.8 V digital supply voltage DTC 3.3 V supply voltage DTC 1.8 V supply voltage
Table 15: Symbol VDDE VSSE VDDI VSS VDDM
[1] [1]
30,35,53,67, 80,97 29,36,43, 54,68,81, 98,139 44,140 1 16 100 101 23 24
VSSD(I2D) VDDD(I2D) VSS(ADAC) VDDD(ADAC) VDD3(DTC) VDDD(DTC)
[1]
VDDI and VDDM can be connected to same 1.8 V supply voltage.
Table 16: Symbol VSSA(I2D) VDDA(I2D) VDDA(PLL) VDDA(ADAC) VSS(DTC) VDDA(XTAL)
Analog supply pins Pin 6 11 33 102 25 37 Type GA SA SA GA OSCVDD Description I2D analog ground I2D analog 1.8 V supply voltage phase locked loop 1.8 V supply voltage audio DAC 3.3 V supply voltage DTC analog ground 1.8 V crystal oscillator supply voltage
7. Functional description
7.1 Overview
Table 17 describes the functions of the hardware blocks (see also PNX2000 Block Diagram Figure 1). For more detailed functional description refer to the PNX2000 User Manual.
Table 17: Function High speed data link Video decoder processor Serial interface Global Task Unit Block function Block I2D VIDDEC I2C-bus GTU Description Receives data in three streams from PNX3000. Decodes and processes CVBS, YUV or Y/C in YUV stream. To access all the internal registers. Generates all the internal clocks, reset and power management.
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PNX2000
Audio video input processor
Block function...continued Block DEMDEC DSP AUDIO DSP DCU ITU-656 BCU Description Demodulation, decoding of terrestrial TV audio standards . Processing analog and digital audio sources. Acquires VBI data (Teletext; CC; VPS) and formats in a stream. Formats YUV, VBI data and CVBS data in ITU-656. Bus arbitration among all the internal blocks.
Table 17: Function
TV sound decoder Audio processor Data Capture Unit Formatter unit Bus Control Unit
7.2 Interfaces
Table 18: Interface I2C-bus I2 D I2S-bus Interfaces Description The PNX2000 IC is controlled using an I2C-bus. It performs like an I2C-bus to PI-bus bridge, i.e. translates I2C-bus slave received commands to PI-bus master commands. Receives data in three streams from PNX3000. Serial digital audio interface (6 stereo inputs, 6 stereo outputs) for connection to other devices that support the I2S-bus standard. Can be used to receive decoded sound from a multi-channel digital audio decoder, provide additional ADCs and DACs, or loop audio signals through an external processor or delay line. Mainly intended to transfer output data stream externally to the PNX8550, but the output data stream could also be readable by other ITU-656 input devices that implement data valid signalling. Digital-analog converters used to generate analog outputs from Sound Core.
ITU-656
DACS
7.3 Features in detail
7.3.1 Video
* * * *
Automatic Gain Control (AGC) to correct amplitude errors at input source. Synchronization identification (used for channel search). Sync processing for 1fH and 2fH video input source. Standard detection of PAL, NTSC or SECAM and various 1fH and 2fH component video input sources.
1fH video
* * * *
Color decoding (ITU-601) for PAL, NTSC or SECAM input sources. 2D comb filtering. Support for component video sources with sync on CVBS or green. Fastblank insertion of RGB signals onto CVBS input.
2fH video
* Support for various progressive and interlaced component video sources. * Synchronization of video sources with sync on Y or external H/V inputs.
VBI data capture
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PNX2000
Audio video input processor
* Decoding of 525 line standards; WST, WSS, VPS, CC, VITC. * Decoding of 625 line standards; WST, WSS, CC, VITC.
ITU-656 output interface
* Video and VBI formatting into ITU-style output data stream, compliant to
ITU-656/1364 (exception being the use of a data valid signal).
* Interfacing to PNX8550 IC. * Support for CVBS/C mode to interface to external picture improvement devices.
7.3.2 Audio
Demodulator and decoder
* * * *
Demodulator and Decoder Easy Programming (DDEP). Auto Standard Detection (ASD). Static Standard Selection (SSS). DQPSK demodulation for different standards, simultaneously with 1-channel FM demodulation.
* NICAM decoding (B/G, I, D/K and L standard). * Two-carrier multi-standard FM demodulation (B/G, D/K and M standard). * Decoding for three analog multi-channel systems (A2, A2+ and A2*) and satellite
sound.
* Adaptive de-emphasis for satellite FM. * Optional AM demodulation for system L, simultaneously with NICAM. * Identification A2 systems (B/G, D/K and M standard) with different identification time
constants.
* FM pilot carrier present detector. * Monitor selection for FM/AM DC values and signals, with peak and quasi peak
detection option.
* * * * * * * *
BTSC MPX decoding. SAP decoding. dbx(R) 3 TV noise reduction. Japan (EIAJ) decoding. FM radio decoding. Soft muting for DEMDEC outputs DEC, MONO and SAP. FM over modulation adaptation option to avoid clipping and distortion. Sample Rate Conversion (SRC) for up to three demodulated terrestrial audio signals. Allows processing of SCART and demodulated terrestrial signals.
Audio multi-channel decoder
* Dolby Pro Logic IITM
3.
dbx is a registered trademark of Carillon Electronics Corp.
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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Philips Semiconductors
PNX2000
Audio video input processor
* 6-channel processing for Main Left and Main Right, Subwoofer, Center, Surround Left
and Surround Right. Volume and tone control
* * * * * * * * * * * * *
Automatic Volume Level (AVL) control. Smooth volume control. Master volume control and balance. Soft mute. Loudness. Bass, treble. Dynamic Bass Enhancement (DBE). Dynamic ULTRABASS (DUB). Non-processed subwoofer. 5-band equalizer. Acoustical compensation. Programmable beeper. Noise generation for loudspeaker level trimming.
Reflection and delay
* Dolby Pro Logic IITM delay. * Pseudo hall/matrix function.
Psychoacoustic spatial algorithms, downmix and split
* * * * * *
Incredible Mono. Incredible Stereo. Virtual Dolby SurroundTM. Virtual Dolby DigitalTM. Bass Redirection according to DolbyTM specifications. BBE(R) Sound Processing 4
Interfaces and switching
* * * * * * * *
4.
Digital audio input interface (stereo I2S-bus input interface). Digital audio output interface (stereo I2S-bus output interface). Digital crossbar switch for all digital signal sources and destinations. Output crossbar for exchange of channel processing functionality. Voice recognition output interface (stereo I2S-bus output interface). Audio monitoring for level detection. Eight audio DACs for 6-channel loudspeaker outputs and stereo headphones output. Four audio DACs for stereo SCART output and stereo LINE output.
BBE is a registered trademark of BBE Sound Inc. See Section 18.
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Philips Semiconductors
PNX2000
Audio video input processor
* Serial data link interfacing for analog multi-purpose interface PNX3000.
8. Television application
Figure 3 shows an overview of the top level hardware architecture of a TV application, using the PNX3000 and PNX2000 as an analog front-end and the PNX8550 as the main processor. This system is aimed at the hybrid (analog or digital) TV market. The main SOC in the system, PNX8550, performs key features for high quality television like video quality enhancement, motion compensation and picture-in-picture processing. PNX2000 together with PNX3000 are used to perform the input decoding of a single stream of analog audio and a single stream of analog video (1fH or 2fH) broadcast signals. PNX2000 performs the following main functions:
* * * * * *
Color decoding into ITU-601 compatible format (1fH or 2fH). A digital interface to external 3D comb filter. VBI data capture (Teletext, WSS, CC). ITU-656 formatting for communication to PNX8550. Audio demodulation and decoding. Audio processing and D-A conversion.
The audio data is transferred between PNX2000 and PNX8550 using I2S-bus. PNX2000 and PNX3000 are controlled from PNX8550 via the I2C-bus.
CVBS SIF VIF I2D L/R audio YUV (656) audio I2S-bus
2 PNX2000 audio I S-bus PNX8550
RGB 10 bits (3x) RGB AMPLIFIER
SCART
21 20 19 20 17 18 15 14 16 13 12 14 11 10 12 18 16 8 6 4 2 10 9 8 7 6 5 4 3 2 1 21 19 17 15 13 11
TUNERS UV1316 UV13361
(2x)
DISPLAY PROCESSOR
CVBS Y/C RGB 2 L/R audio 2 CVBS 1 L/R audio 1
PNX3000
audio I2S-bus (3x)
DEFL. CONT.
32-bit
DDR 16 Mb
8-bit or 16-bit status
FLASH ROM 18 Mb
LEVEL ADJUSTMENT STANDBY MICROCONTROLLER AUDIO AMPLIFIER
mce558
REMOTE CONTROL
LOCAL KEYPAD
Fig 3. TV application
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9. Limiting values
Permanent damage may occur if absolute maximum ratings are exceeded. Prolonged operation at maximum rating may significantly reduce the reliability of the product.
Table 19: Absolute maximum ratings Ratings are valid only within operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise stated. Symbol VDD(core) VDD(I/O) VI VI Ilatchup Vesd Vesd Tstg
[1] [2] [3] [4] [5] [6] [7]
Parameter supply voltage supply voltage DC input voltage ( [1] [2] and
[3])
Min -0.5 -0.5 -0.5 ( [2] and [3])
[7])
Max +2.5 +4.6 VDD(I/O) + 0.5 +6 2 200 +125
Unit V V V V mA kV V C
DC input voltage 5V tolerant I/O pins latch-up current ( [4])
-0.5 100 -40
electrostatic discharge voltage HBM ( [5] and electrostatic discharge voltage MM storage temperature ( [6]
and [7])
Not to exceed 4.6 V. Including voltage on outputs in 3-state mode. Only valid when the VDD(I/O) supply voltage is present. Valid for : -(0.5 x VDD) < V < +(1.5 x VDD); Tj < 125 C. Human Body Model, Ileak < 1 mA. Machine Model 0.5 mH, Ileak < 1 mA. This product includes circuits specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. However, it is suggested that conventional precautions be taken to avoid applying voltages greater than the rated maximum.
10. Characteristics
10.1 Static characteristics
Table 20: Static characteristics: power supply pins Tamb = 0 C to +70 C to commercial unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit
1.8V Power Supply Pins: VDDI, VDDM, VDDD(I2D), VDDA(I2D), VDDA(PLL), VDDA(XTAL), VDDD(ADAC), VDDD(DTC) VDD(core) IDD(core) supply voltage, 1.8 V supplies supply current, 1.8 V supplies VDD(core) = 1.8 V 1.65 1.8 250 1.95 V mA
3.3V Power Supply Pins: VDDE, VDD3(DTC), VDDA(ADAC) VDD(3V3) IDD(3V3) supply voltage, 3.3 V supplies supply current, 3.3 V supplies VDD(core) = 3.3 V 3.0 3.3 50 3.6 V mA
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Table 21: Static characteristics: digital pins Tamb = 0 C to +70 C to commercial unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit
I2S inputs: I2S_IN_SD1-6, I2C Address: I2C_ADR IIL VI VIH VIL IPD IIL IIH VI VIH VIL IIH VI VIH VIL Vhys IPU LOW-level input current input voltage HIGH-level input voltage LOW-level input voltage pull-down current LOW-level input current HIGH-level input current input voltage HIGH-level input voltage LOW-level input voltage HIGH-level input current input voltage HIGH-level input voltage LOW-level input voltage hysteresis voltage pull-up current Vi = 0 Vi = VDD(I/O) Vi = 0 Vi = VDD(I/O) Vi = VDD(I/O) Vi = 0 VDD(I/O) < Vi < 5 V I2C Pins: I2C_SDA, I2C_SCL CI ILI IIN(MAX) VI VIL VIH VOL IOL Ioz VI VOH VOL IOH IOL IOH IOL input capacitance input leakage current [1] max. input current [2] input voltage LOW-level input voltage HIGH-level input voltage LOW-level output voltage LOW-level output current 3-state output leakage input voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current HIGH-level short circuit current LOW-level short circuit current VDD(3V3) = 3.3 V; Tamb = 25 C at 5 V VOL=0.4V VO = 0 VO = VDD(I/O) IOH = -4 mA IOL = 4 mA VOH = 2.4 VOL = 0.4 V VOH = 0 VOL = VDD(I/O) 1.37 8.20 0 2.0 0 2.4 -4 4 5 1.85 10.7 8.45 2.45 12.45 5 0.8 0.4 1 5.5 0.4 -45 50 pF A A V V V V mA A V V V mA mA mA mA 0 2.0 20 0 2.0 0 2.0 -25 0 50 0.3 -50 0 1 5.5 0.8 75 1 1 5.5 0.8 1 5.5 0.8 -65 0 A V V V A A A V V V A V V V V A A
External Sync: VSYNC1, VSYNC2, Reset: RESET_SEL, ITU-656: LL_CLK
Jtag inputs: TDI, TCK, TRST_N, TMS
ITU-656 Outputs: DVO_DATA_0-9, DVO_VALID, DVO_CLK
I2S I/O: I2S_SCK_SYS, I2S_WS_SYS
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Table 21: Static characteristics: digital pins...continued Tamb = 0 C to +70 C to commercial unless otherwise specified. Symbol IIL IIH VI VIH VIL Vhys Ioz VOH VOL IOH IOL IOH IOL VOH VOL IOH IOL IOH IOL VOH VOL IOH IOL IOH IOL Ioz VI VOL IOL IOL Parameter LOW-level input current HIGH-level input current input voltage HIGH-level input voltage LOW-level input voltage hysteresis voltage 3-state output leakage HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current HIGH-level short circuit current LOW-level short circuit current HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current HIGH-level short circuit current LOW-level short circuit current HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current HIGH-level short circuit current LOW-level short circuit current 3-state output leakage input voltage LOW-level output voltage LOW-level output current LOW-level short circuit current Conditions Vi = 0 Vi = VDD(I/O) VO = 0 VO = VDD(I/O) IOH = -8 mA IOL = 8 mA VOH = 2.4 VOL = 0.4 V VOH = 0 VOL = VDD(I/O) IOH = -4 mA IOL = 4 mA VOH = 2.4 VOL = 0.4V VOH = 0 VOL = VDD(I/O) IOH = -8 mA IOL = 8 mA VOH = 2.4 VOL = 0.4 V VOH = 0 VOL = VDD(I/O) VO = 0 VO = VDD(I/O) IOL = 8 mA VOL = 0.4 V VOL = VDD(I/O) Min 0 2.0 2.4 -8 8 2.4 -4 4 2.4 -8 8 0 8 Typ 0.4 Max 1 1 VDD(I/O) 0.8 1 0.4 -95 95 0.4 -45 50 0.4 -95 95 1 5.5 0.4 140 Unit A A V V V V A V V mA mA mA mA V V mA mA mA mA V V mA mA mA mA A V V mA mA
I2S Outputs: I2S_OUT_SD1-6, JTAG Output: TDO, PNX3000 Clock: MPIFCLK, Sync Output: HVINFO
I2S Output: I2S_OUT_SD3_SCK, I2S_OUT_SD3_WS, ADAC_CLK, Clock Output: DCLK
Interrupt: INTOUT
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Table 22: Static characteristics: analog pins Tamb = 0 C to +70 C to commercial unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit
External Sync: HSYNCFBL1, HSYNCFBL2 VIT VIT Vtrip_high Vtrip_low I2D Zdiff VDATA(pos) VDATA(neg) VSTROBE(pos) VSTROBE(neg) Vsens input threshold input threshold high trip level low trip level input sensitivity differential line load impedance data pos. range data neg. range strobe pos. range strobe neg. range positive reference voltage negative reference voltage positive reference current output voltage (rms); single-ended, digital i/p level = 0 dBFS output resistance load resistance dtc_lowth = 0 dtc_lowth = 1 RESET_SEL = 0 RESET_SEL = 0 across input diff pair 1.0 0.95 0 0 0 0 3.0 0.7 10 1.65 0.65 1.2 1.1 6 100 3.3 0 820 1.17 1.0 1.4 1.3 300 300 300 300 3.6 1.3 V V V V mV mV mV mV mV V V A V k k
Reset: RESET_N
Inputs: DLINK1-3DP, DLINK1-3DN,DLINK1-3SP, DLINK1-3SN
Audio DACs: ADAC1-12P, ADAC1-12N
VREFP VREFN IREFP VOUT(rms) ROUT RL
Audio DACs: ADAC1-12
10.2 Dynamic characteristics
Table 23: Symbol I2C fclk tr tf clock frequency rise time fall time 1.5 k ext. pull-up; 160 pF load 1.5 k ext. pull-up; 160 pF load 130 400 550 162 245 kHz ns ns Dynamic characteristics Parameter Conditions Min Typ Max Unit
Viddec: HVINFO (slew rate limited) tthl ttlh ITU-656 tsu(DATA) data setup at Rx 40 pF load 7.3 ns output transition time (H to L) output transition time (L to H) 30 pF load 30 pF load 10 10 13.8 13.8 ns ns
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Table 23: Symbol th(DATA) I2S fs fSCK fSCK DFSCK DFSCK tRSCK tRSCK td th ts I2D
Dynamic characteristics...continued Parameter data hold at Rx Conditions 40 pF load Min Typ Max 4.9 Unit ns
audio sample frequency SCK frequency SCK frequency SCK duty factor SCK duty factor SCK rise / fall time SCK rise / fall time delay time: SCK to WS and SD outputs [2]
I2S-bus master mode I2S-bus slave mode I2S-bus master mode I2S-bus slave mode I2S-bus master mode; Cload = 30 pF
32 32fs 40 35 -
48 64fs 64fs 50 0.5 -
48 256fs 60 65 5 50 0.7 -
kHz % % ns ns TSCK ns TSCK
I2S-bus slave mode; fSCK = 3.072 MHz TSCK = 1/fSCK 0.3 0 0.2
hold time: SCK to WS and SD inputs setup time: WS and SD inputs to SCK TSCK = 1/fSCK
fclock(WORD) word clock frequency WL DR fclock(BIT) word length data rate bit clock freq.
-
-
13.5 44 594 297
-
MHz bit Mbit/s MHz
JTAG Clock Reset tlow thigh Time RESET_N should be below Vtrip_high before internal reset = 1. Time RESET_N should be above Vtrip_high before internal reset = 0 (after tpulse). Time before PNX2000 internal reset = 0 [3]. RESET_SEL = 0 RESET_SEL = 0 11 2 s s
tpulse
RESET_SEL = 0
200
-
-
ns
[1] [2] [3]
Allowed SCK/WS ratios are 32, 48, 64, 128 and 256 SCK periods per WS period. All timings relative to the rising edge of SCK. See Section 10.4 for waveforms.
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10.3 Audio DAC characteristics
Table 24: Dynamic characteristics: Audio DAC Tamb = 0 C to +70 C for commercial unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit
Audio DAC Outputs: ADAC1-12 fs S/N audio sample frequency Signal to Noise Ratio, CCIR-2 k weighted outputs muted; reference f = 2 kHz, 0 dBFS f =1 kHz; 0 dBFS; 22 kHz measurement bandwidth +/-1 dB f = 1 kHz; 0 dBFS 32 <10 48 [1] 94 -77 -90 48 22.5 kHz dB dB kHz dB
(THD+N)/S Total Harmonic Distortion + Noise to Signal ratio fres ct
[1]
frequency response crosstalk between adjacent DACs
Allowed audio sample frequencies are 32 kHz, 44.1 kHz and 48 kHz. Default fS in I2S-bus master mode is 48 kHz.
The audio DACs are based on a switched-resistor architecture which acts as a controlled voltage divider between the positive and negative references ADACn_P and ADACn_N. Therefore all noise on the reference pins will spread directly to the associated output pin ADACn. Consequently it is important to provide adequate filtering of the reference voltage to allow optimum signal-to-noise performance. Also, the voltage difference between ADACn_P and SDAC_3V3 should be kept to a minimum as any difference will degrade distortion performance. The DACs have an internal resolution of 4 bits, running at a clock frequency of 128 fS, using a noise shaper circuit to shift the quantization noise to out-of-band frequencies. To prevent HF overloading of the circuit that is driven by the DAC outputs, a 3.3 nF capacitor should be used to filter off the HF signal content. Together with the DAC's nominal output impedance of 1 k, a first order roll-off at approximately 50 kHz will result. One capacitor is required for each DAC output, connected between ADACn and the corresponding ADACn_N.
10.4 Timing
10.4.1 Clock
Crystal specification The crystal oscillator can be used with an external crystal, or in bypass mode with external clock signal, see Figure 4.
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VDDA
VSSA
pd
xtm
VDDA
VSSA
pd
xtm
XO
on-chip osc_in osc_out n.c. off-chip (a) clock
clkout
XO
clkout
osc_in
osc_out
(b) Cx1 Cx2
mce560
Fig 4. Application diagram: (a) slave/test mode, (b) oscillation mode
The supported crystal/external clock frequencies are 27 MHz and 13.5 MHz. The crystal oscillator is followed by a selectable divide-by-two frequency divider giving three available clock frequencies, as shown in Table 25.
Table 25: 27 MHz 27 MHz 13.5 MHz 13.5 MHz Primary clock settings Divider setting x/1 x/2 x/1 x/2 Clock frequency 27 MHz 13.5 MHz 13.5 MHz 6.75 MHz
Clock/Crystal Input
The crystal specification is:
* * * * *
Package: surface mount. Accuracy: (50 ppm). Temperature: (50 ppm). Operating temperature range: -20 to +70 oC. Load capacitance: 30 pF.
Crystal parameters Crystal load capacitance (CL) 10 pF 20 pF 30 pF Max.crystal series resistance (RS) < 600 < 255 < 140 < 130 < 50 n.a. External load capacitors (Cx1; Cx2) 2 x 18 pF 2 x 38 pF 2 x 58 pF 2 x 18 pF 38 pF; 18 pF n.a.
Table 26: Oscillator
frequency (fc) 13.5 MHz
27 MHz 10 pF 20 pF 30 pF
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10.4.2 Reset
long external reset produces internal reset short spike ignored
RESET_N
tlow
tpulse
internal reset
thigh
mce561
RESET_N pin and internal reset timing
Fig 5. PNX2000 reset
10.4.3 ITU-656
DVO_CLK
DVO_DATA[9:0]
DVO_VALID tsu(DATA) th(DATA)
mce562
Fig 6. Timing ITU interface
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11. Glossary
AGC................. Automatic Gain Control ASD ................. Auto Standard Detection AVL.................. Auto Volume Level BCU................. Bus Control Unit BTSC............... Broadcast TV System Committee DBE ................. Dynamic Base Enhancement DCU................. Data Capture Unit DDEP .............. Demodulator and Decoder Easy Programming DEMDEC ......... Demodulator Decoder DQPSK............ Differential Quadrature Phase Shift Keying DSP ................. Digital Signal Processor DUB................. Dynamic UltraBass DVD ................. Digital Video Disc EIAJ ................ Electronic Industries Association of Japan GTU ................. Global Task Unit HBM ................ Human Body Model LQFP ............... Low profile Quad Flat Package MM .................. Machine Model MPX................. Multiplexer NICAM............. Near Instantaneous Compounded Audio Multiplex NTSC............... National TV Systems Committee PAL.................. Phase Alternate Line SAP ................. Secondary Audio Program SCART ............ Syndicate for Constructors of Apparatus for Radio and Television SECAM ........... Sequential Color and Memory SMD ................ Surface Mount Device SRC ................. Sample Rate Conversion SSS ................. Static Standard Selection SSOP...............Shrink Small Outline Package SOC .................System On Chip VBI...................Vertical Blanking Interval VIDDEC ...........Video front-end Decoder VITC.................Vertical Interval Time Code VPS..................Video Program System WSS.................Wide Screen Signaling WST.................World System Teletext
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12. Package outline
LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm SOT486-1
c
y X
A 108 109 73 72 ZE
e
E HE
A A2
A1
(A 3) Lp L detail X
wM bp pin 1 index 144 1 wM D HD ZD B vM B 36 bp vM A 37
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT486-1 REFERENCES IEC 136E23 JEDEC MS-026 JEITA EUROPEAN PROJECTION A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 20.1 19.9 E (1) 20.1 19.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 Z D(1) Z E(1) 1.4 1.1 1.4 1.1 7 o 0
o
22.15 22.15 21.85 21.85
ISSUE DATE 00-03-14 03-02-20
Fig 7. LQFP package outline
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13. Soldering
13.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. In these situations reflow soldering is recommended.
13.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:
* below 220 C (SnPb process) or below 245 C (Pb-free process)
-- for all BGA and SSOP-T packages -- for packages with a thickness 2.5 mm -- for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages.
* below 235 C (SnPb process) or below 260 C (Pb-free process) for packages with a
thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
13.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
* Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
* For packages with leads on two sides and a pitch (e):
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-- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; -- smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle to
the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
13.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
13.5 Package related soldering information
Table 27: Package [1] Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave BGA, LBGA, LFBGA, SQFP, SSOP-T [3], TFBGA, not suitable VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, not suitable [4] HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC [5], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP PMFP [8]
[1] [2]
Reflow [2] suitable suitable suitable suitable suitable not suitable
suitable not recommended [5] [6] not recommended [7] not suitable
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods.
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[3]
These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. Hot bar or manual soldering is suitable for PMFP packages.
[4]
[5] [6] [7] [8]
14. Revision history
Table 28: Rev Date 03 02 01 20040823 20040712 20040504 Revision history CPCN Description Minor revision (9397 750 13928) Upgraded to Product data (9397 750 13591). Table 3 and Table 4 added. Preliminary data (9397 750 12066)
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15. Data sheet status
Level I II Data sheet status [1] Objective data Product status [2] [3] Development Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Preliminary data Qualification
III
Product data
Production
[1] [2]
Consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status
[3]
18. Licenses
Purchase of Philips I2C components Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. Dolby Laboratories `Dolby' and `Pro Logic' are trademarks of Dolby Laboratories, San Francisco, USA. Products are available to licensees of Dolby Laboratories Licensing Corp., 100 Potrero Avenue, San Francisco, CA, 94103, USA. Tel: 1-415-558-0200, Fax: 1-415-863-1373. Supply of this implementation of Dolby Technology does not convey a license, nor imply a right under any patent to use this implementation in any final product. A license for such use is required from Dolby Laboratories. BBE Sound
16. Definitions
Short-form specification - The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition - Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information - Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
17. Disclaimers
Life support - These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes - Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these
BBE is a registered trademark of BBE Sound Inc., 5381 Production Drive, Huntington Beach, CA, 92649, USA. The use of BBE needs licensing from BBE Sound Inc. Tel: 1-714-897-6766, Fax: 1-714-895-6728. dbx - TV noise reduction A Set-Maker License is required for use of this product under one (or more) of the following patents: US4,539,526; 5,796,842; 6,118,879 and U.S. Patent Application 09/638245 . For further information contact THAT Corporation, 45 Sumner Street, Milford, Massachusetts 01757-1656, USA. Tel: 1-508-478-9200, FAX: 1-508-478-0990
19. Trademarks
Nexperia - is a trademark of Koninklijke Philips Electronics N.V. Dolby Pro Logic,Virtual Dolby Digital and Virtual Dolby Surround - are trademarks of Dolby Laboratories |nc. BBE - is a registered trademark of BBE Sound Inc. dbx - is a registered trademark of Carillon Electronics Corp.
20. Contact information
For additional information, please visit http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 13928 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 - 23 August 2004
30 of 31
Philips Semiconductors
PNX2000
Audio video input processor
21. Contents
1 2 3 4 5 6 6.1 6.1.1 7 7.1 7.2 7.3 7.3.1 7.3.2 8 9 10 10.1 10.2 10.3 10.4 10.4.1 10.4.2 10.4.3 11 12 13 13.1 13.2 13.3 13.4 13.5 14 15 16 17 18 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . 12 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Features in detail . . . . . . . . . . . . . . . . . . . . . . 13 Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Audio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Television application . . . . . . . . . . . . . . . . . . . 16 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 17 Static characteristics. . . . . . . . . . . . . . . . . . . . 17 Dynamic characteristics . . . . . . . . . . . . . . . . . 20 Audio DAC characteristics . . . . . . . . . . . . . . . 22 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 ITU-656. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 26 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 27 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 27 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 28 Package related soldering information . . . . . . 28 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 29 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 30 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Contact information . . . . . . . . . . . . . . . . . . . . 30
(c) Koninklijke Philips Electronics N.V. 2004
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 23 August 2004 Document order number: 9397 750 13928
Published in Netherlands

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